Programmable counters have been in use for many years. With most prior art units it takes 16 programming bits to insert a preset word into a 16-bit digital counter. In other prior art units a Read--Only--Memory is used. The former has the disadvantage of requiring an N+ 1 bit data word for programming 2.sup.N steps while the latter method is not economical for low volume applications due to the requirement for a customized Read--Only--Memory. My invention utilizes standard medium scale integrated circuit logic modules to implement the system. With my invention, the number of programming bits required to preset the counter circuitry is reduced from N+ 1 bits to the number of bits required to represent the number N in binary form.
Possible applications include its use in a peripheral controller such as those used in Rotary Machinery Analysis Systems. There time-domain data is often converted to frequency-domain data. This requires that the block size of the data samples be taken in time increments having a 2.sup.N binary relationship.